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M48Z128 M48Z128Y, M48Z128V*
5.0V OR 3.3V, 1 Mbit (128 Kbit x 8) ZEROPOWER(R) SRAM
FEATURES SUMMARY s INTEGRATED, ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT, and BATTERY
s
Figure 1. 32-pin PMDIP Module
CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES 10 YEARS OF DATA RETENTION IN THE ABSENCE OF POWER BATTERY INTERNALLY ISOLATED UNTIL POWER IS FIRST APPLIED AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION WRITE PROTECT VOLTAGES: (VPFD = Power-fail Deselect Voltage) - M48Z128: VCC = 4.75 to 5.5V 4.5V VPFD 4.75V - M48Z128Y: VCC = 4.5 to 5.5V 4.2V VPFD 4.5V - M48Z128V: VCC = 3.0 to 3.6V 2.8V VPFD 3.0V SOIC PACKAGE PROVIDES DIRECT CONNECTION FOR A SNAPHAT TOP WHICH CONTAINS THE BATTERY SNAPHAT HOUSING (BATTERY) IS REPLACEABLE PIN and FUNCTION COMPATIBLE WITH JEDEC STANDARD 128K x 8 SRAMs EQUIVALENT SURFACE-MOUNT (SMT) SOLUTION REQUIRES A 28-PIN M40Z300/W and A STAND-ALONE 128K x8 LPSRAM (SNAPHAT(R) Top to be ordered separately)
32 1
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PMDIP32 (PM) Module
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* Contact Local Sales Office
October 2003
Rev. 3.4
1/21
M48Z128, M48Z128Y, M48Z128V*
TABLE OF CONTENTS DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Logic Diagram (Figure 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Signal Names (Table 1.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 DIP Connections (Figure 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Block Diagram (Figure 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Hardware Hookup for Equivalent Surface-Mount (SMT) Solution (Figure 5.) . . . . . . . . . . . . . . . . . . 5 Equivalent Surface-Mount (SMT) Solution (Table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute Maximum Ratings (Table 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Operating and AC Measurement Conditions (Table 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 AC Measurement Load Circuit (Figure 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Capacitance (Table 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 DC Characteristics (Table 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Operating Modes (Table 7.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Chip Enable or Output Enable Controlled, READ Mode AC Waveforms (Figure 7.). . . . . . . . . . . . . 9 Address Controlled, READ Mode AC Waveforms (Figure 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 READ Mode AC Characteristics (Table 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 WRITE Enable Controlled, WRITE AC Waveforms (Figure 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Chip Enable Controlled, WRITE AC Waveforms (Figure 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 WRITE Mode AC Characteristics (Table 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Data Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power Down/Up Mode AC Waveforms (Figure 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power Down/Up AC Characteristics (Table 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power Down/Up Trip Points DC Characteristics (Table 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 VCC Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Supply Voltage Protection (Figure 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 SNAPHAT Battery Table (Table 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2/21
M48Z128, M48Z128Y, M48Z128V*
DESCRIPTION The M48Z128/Y/V ZEROPOWER(R) RAM is a 128 Kbit x 8 non-volatile static RAM organized as131,072 words by 8 bits. The device combines an internal lithium battery, a CMOS SRAM and a control circuit in a plastic, 32-pin DIP module. This solution is available in two special packages to provide a highly integrated battery backed-up memory solution. The M48Z128/Y/V is a non-volatile pin and function equivalent to any JEDEC standard 128K x 8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the non-volatility of PROMs without any requirement for special WRITE timing or limitations on the number of WRITEs that can be performed. The 32-pin, 600mil DIP Module houses the M48Z128/Y/V silicon with a long life lithium button cell in a single package. For surface-mount environments ST provides an equivalent SMT solution consisting of a 28-pin, 330mil SOIC NVRAM SUPERVISOR (M40Z300/
W) and a 32-pin, (TSOP, 8 x 20mm) 1Mb LPSRAM. Both 5V and 3V versions are available (see Table 2, page 5). The 28-pin, 330mil SOIC provides sockets with gold plated contacts at both ends for direct connection to a separate SNAPHAT(R) housing containing the battery. The unique design allows the SNAPHAT battery package to be mounted on top of the SOIC package after the completion of the surface-mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery damage due to the high temperatures required for device surfacemounting. The SNAPHAT housing is keyed to prevent reverse insertion. The SNAPHAT battery package is shipped separately in plastic anti-static tubes or in Tape & Reel form. The part number is "M4Zxx-BR00SH" (see Table 13, page 15).
Figure 2. Logic Diagram
VCC
Table 1. Signal Names
A0-A16 DQ0-DQ7 Address Inputs Data Inputs / Outputs Chip Enable Input Output Enable Input WRITE Enable Input Supply Voltage Ground Not Connected Internally
17 A0-A16 M48Z128 M48Z128Y M48Z128V
8 DQ0-DQ7
E G W VCC VSS NC
W E G
VSS
AI01194
3/21
M48Z128, M48Z128Y, M48Z128V*
Figure 3. DIP Connections
NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 32 1 31 2 30 3 29 4 28 5 27 6 26 7 M48Z128 25 8 M48Z128Y 24 9 M48Z128V 23 10 22 11 21 12 20 13 19 14 18 15 17 16
AI01195
VCC A15 NC W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
Figure 4. Block Diagram
VCC
A0-A16
POWER E VOLTAGE SENSE AND SWITCHING CIRCUITRY
131,072 x 8 SRAM ARRAY
DQ0-DQ7
E W G
INTERNAL BATTERY
VSS
AI01196
4/21
M48Z128, M48Z128Y, M48Z128V*
Figure 5. Hardware Hookup for Equivalent Surface-Mount (SMT) Solution
THS(1,2) SNAPHAT (3) BATTERY
VOUT
VCC E2
M40Z300/W E E1CON E2CON E3CON E4CON A RST B BL VSS
1Mb LPSRAM DQ0-DQ7 E
A0-A16
W VSS
AI03625
Note: For pin connections, see individual data sheet for M48Z300/300W at www.st.com. 1. Connect THS pin to VOUT if 4.2V VPFD 4.5V (M48Z128Y) or connect THS pin to VSS if 4.5V VPFD 4.75V (M48Z128). 2. Connect THS pin to VSS if 2.8V VPFD 3.0V (M48Z128V). 3. SNAPHAT(R) Top ordered separately.
Table 2. Equivalent Surface-Mount (SMT) Solution
NVRAM M48Z128 M48Z128Y M48Z128V LPSRAM 5V 1Mb LPSRAM 5V 1Mb LPSRAM 3V 1Mb LPSRAM SUPERVISOR M40Z300 M40Z300 M40Z300W THS Pin(1) VSS VOUT VSS
Note: 1. Connection of Threshold Select Pin (Pin 13) of SUPERVISOR (M40Z300/300W).
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M48Z128, M48Z128Y, M48Z128V*
MAXIMUM RATING Stressing the device above the rating listed in the "Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is Table 3. Absolute Maximum Ratings
Symbol TA TSTG TBIAS TSLD(1,2) VIO VCC IO PD Parameter Ambient Operating Temperature Storage Temperature (VCC Off, Oscillator Off) Temperature Under Bias Lead Solder Temperature for 10 seconds Input or Output Voltages M48Z128/Y Supply Voltage M48Z128V Output Current Power Dissipation -0.3 to 4.6 20 1 V mA W Value 0 to 70 -40 to 85 -10 to 70 260 -0.3 to 7 -0.3 to 7.0 Unit C C C C V V
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Note: 1. For DIP package: Soldering temperature not to exceed 260C for 10 seconds (total thermal budget not to exceed 150C for longer than 30 seconds). 2. For SO package: Reflow at peak temperature of 215C to 225C for < 60 seconds (total thermal budget not to exceed 180C for between 90 to 120 seconds).
CAUTION: Negative undershoots below -0.3V are not allowed on any pin while in the Battery Back-up mode. CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
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M48Z128, M48Z128Y, M48Z128V*
DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters.
Table 4. Operating and AC Measurement Conditions
Parameter Supply Voltage (VCC) Ambient Operating Temperature (TA) Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages M48Z128/Y 4.75 to 5.5V or 4.5 to 5.5 0 to 70 100 5 0 to 3 1.5 M48Z128V 3.0 to 3.6 0 to 70 50 5 0 to 3 1.5 Unit V C pF ns V V
Note: Output Hi-Z is defined as the point where data is no longer driven.
Figure 6. AC Measurement Load Circuit
DEVICE UNDER TEST
650
CL = 100pF or 50pF(1)
1.75V
CL includes JIG capacitance
Note: 1. 50pF for M48Z128V (3.3V).
AI03630
Table 5. Capacitance
Symbol CIN CIO(3) Parameter(1,2) Input Capacitance Input / Output Capacitance Min Max 10 10 Unit pF pF
Note: 1. Effective capacitance measured with power supply at 5V (M48Z128/Y) or 3.3V (M48Z128V); sampled only, not 100% tested. 2. At 25C, f = 1MHz. 3. Outputs deselected.
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M48Z128, M48Z128Y, M48Z128V*
Table 6. DC Characteristics
M48Z128/Y Sym Parameter Test Condition(1) -70 / -85 / -120 Min ILI ILO(2) ICC ICC1 ICC2 VIL VIH VOL VOH Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby) TTL Supply Current (Standby) CMOS Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 2.1mA IOH = -1mA 2.4 0V VIN VCC 0V VOUT VCC E = VIL Outputs open E = VIH E = VCC - 0.2V -0.3 2.2 Max 1 1 105 7 4 0.8 VCC + 0.3 0.4 2.2 -0.3 2.2 M48Z128V -85 / -120 Min Max 1 1 50 4 3 0.6 VCC + 0.3 0.4 A A mA mA mA V V V V Unit
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 4.75 to 5.5V, 4.5 to 5.5V, or 3.0 to 3.6V (except where noted). 2. Outputs deselected.
OPERATING MODES The M48Z128/Y/V also has its own Power-fail Detect circuit. The control circuitry constantly monitors the single VCC supply for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the SRAM, providing a high degree Table 7. Operating Modes
Mode Deselect WRITE READ READ Deselect Deselect VCC 4.75 to 5.5V or 4.5 to 5.5V or 3.0 to 3.6V VSO to VPFD (min)(1) VSO(1) E VIH VIL VIL VIL X X
of data security in the midst of unpredictable system operation brought on by low VCC. As VCC falls below the switchover voltage (VSO), the control circuitry connects the battery which maintains data until valid power returns.
G X X VIL VIH X X
W X VIL VIH VIH X X
DQ0-DQ7 High Z DIN DOUT High Z High Z High Z
Power Standby Active Active Active CMOS Standby Battery Back-up Mode
Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage. 1. See Table 11, page 14 for details.
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M48Z128, M48Z128Y, M48Z128V*
READ Mode The M48Z128/Y/V is in the READ Mode whenever W (WRITE Enable) is high and E (Chip Enable) is low. The device architecture allows ripple-through access of data from eight of 1,048,576 locations in the static storage array. Thus, the unique address specified by the 17 address inputs defines which one of the 131,072 bytes of data is to be accessed. Valid data will be available at the Data I/O pins within Address Access time (tAVQV) after the last address input signal is stable, providing that the E and G (Output Enable) access times are also sat-
isfied. If the E and G access times are not met, valid data will be available after the later of Chip Enable Access time (tELQV) or Output Enable Access Time (tGLQV). The state of the eight threestate Data I/O signals is controlled by E and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the address inputs are changed while E and G remain low, output data will remain valid for Output Data Hold time (tAXQX) but will go indeterminate until the next Address Access.
Figure 7. Chip Enable or Output Enable Controlled, READ Mode AC Waveforms
tAVAV A0-A16 tAVQV tELQV E tELQX tGLQV G tGLQX DQ0-DQ7 DATA OUT
AI01197
VALID tAXQX tEHQZ
tGHQZ
Note: WRITE Enable (W) = High.
Figure 8. Address Controlled, READ Mode AC Waveforms
tAVAV A0-A16 tAVQV VALID tAXQX
DQ0-DQ7
DATA VALID
AI01078
Note: Chip Enable (E) and Output Enable (G) = Low, WRITE Enable (W) = High.
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M48Z128, M48Z128Y, M48Z128V*
Table 8. READ Mode AC Characteristics
M48Z128/Y Symbol Parameter(1) Min tAVAV tAVQV tELQV tGLQV tELQX(2) tGLQX(2) tEHQZ(2) tGHQZ(2) tAXQX READ Cycle Time Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable Low to Output Transition Output Enable Low to Output Transition Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition 5 5 3 30 20 5 70 70 70 35 5 3 35 25 10 -70 Max Min 85 85 85 45 5 3 45 35 M48Z128/Y/V -85 Max M48Z128/Y/V -120 Min 120 120 120 60 Max ns ns ns ns ns ns ns ns ns Unit
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 4.75 to 5.5V, 4.5 to 5.5V, or 3.0 to 3.6V (except where noted). 2. CL = 5pF.
10/21
M48Z128, M48Z128Y, M48Z128V*
WRITE Mode The M48Z128/Y/V is in the WRITE Mode whenever W and E are active. The start of a WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for minimum of tEHAX from E or tWHAX from W prior to the initiation
of another READ or WRITE cycle. Data-in must be valid tDVWH prior to the end of WRITE and remain valid for tWHDX or tEHDX afterward. G should be kept high during WRITE cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G, a low on W will disable the outputs tWLQZ after W falls.
Figure 9. WRITE Enable Controlled, WRITE AC Waveforms
tAVAV A0-A16 VALID tAVWH tAVEL E tWLWH tAVWL W tWLQZ tWHDX DQ0-DQ7 DATA INPUT tDVWH
AI01198
tWHAX
tWHQX
Note: Output Enable (G) = High.
Figure 10. Chip Enable Controlled, WRITE AC Waveforms
tAVAV A0-A16 VALID tAVEH tAVEL E tAVWL W tEHDX DQ0-DQ7 DATA INPUT tDVEH
AI01199
tELEH
tEHAX
Note: Output Enable (G) = High.
11/21
M48Z128, M48Z128Y, M48Z128V*
Table 9. WRITE Mode AC Characteristics
M48Z128/Y Symbol Parameter(1) Min tAVAV tAVWL tAVEL tWLWH tELEH tWHAX tEHAX tDVWH tDVEH tWHDX tEHDX tWLQZ(2,3) tAVWH tAVEH tWHQX(2,3) WRITE Cycle Time Address Valid to WRITE Enable Low Address Valid to Chip Enable Low WRITE Enable Pulse Width Chip Enable Low to Chip Enable High WRITE Enable High to Address Transition Chip Enable High to Address Transition Input Valid to WRITE Enable High Input Valid to Chip Enable High WRITE Enable High to Input Transition Chip Enable High to Input Transition WRITE Enable Low to Output Hi-Z Address Valid to WRITE Enable High Address Valid to Chip Enable High WRITE Enable High to Output Transition 65 65 5 70 0 0 55 55 5 15 30 30 0 10 25 75 75 5 -70 Max Min 85 0 0 65 75 5 15 35 35 0 10 30 100 100 5 M48Z128/Y/V -85 Max M48Z128/Y/V -120 Min 120 0 0 85 100 5 15 45 45 0 10 40 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 4.75 to 5.5V, 4.5 to 5.5V or 3.0 to 3.6V (except where noted). 2. CL = 5pF. 3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
12/21
M48Z128, M48Z128Y, M48Z128V*
Data Retention Mode With valid VCC applied, the M48Z128/Y/V operates as a conventional BYTEWIDETM static RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself tWP after VCC falls below VPFD. All outputs become high impedance, and all inputs are treated as "Don't care." If power fail detection occurs during a valid access, the memory cycle continues to completion. If the memory cycle fails to terminate within the time tWP, write protection takes place. When VCC drops below VSO, the control circuit switches power to the internal energy source which preserves data. Figure 11. Power Down/Up Mode AC Waveforms
VCC VPFD (max) VPFD (min) VSO tF tFB tWP E
RECOGNIZED
The internal coin cell will maintain data in the M48Z128/Y/V after the initial application of VCC for an accumulated period of at least 10 years when VCC is less than VSO. As system power returns and VCC rises above VSO, the battery is disconnected, and the power supply is switched to external VCC. Write protection continues for tER after VCC reaches VPFD to allow for processor stabilization. After tER, normal RAM operation can resume. For more information on Battery Storage Life refer to the Application Note AN1012.
tDR tRB
tR
tER DON'T CARE
RECOGNIZED
HIGH-Z OUTPUTS VALID
(PER CONTROL INPUT)
VALID
(PER CONTROL INPUT)
AI01031
Table 10. Power Down/Up AC Characteristics
Symbol tF(2) tFB(3) tR tRB tWP tER Parameter(1) VPFD (max) to VPFD (min) VCC Fall Time M48Z128/Y VPFD (min) to VSS VCC Fall Time VPFD (min) to VPFD (max) VCC Rise Time VSS to VPFD (min) VCC Rise Time M48Z128/Y Write Protect Time M48Z128V E Recovery Time 40 40 250 120 ms M48Z128V Min 300 10 s 150 10 1 40 150 s s s Max Unit s
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 4.75 to 5.5V, 4.5 to 5.5V, or 3.0 to 3.6V (except where noted). 2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200s after VCC passes VPFD (min). 3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
13/21
M48Z128, M48Z128Y, M48Z128V*
Table 11. Power Down/Up Trip Points DC Characteristics
Symbol Parameter(1,2) M48Z128 VPFD Power-fail Deselect Voltage M48Z128Y M48Z128V M48Z128/Y VSO tDR(3) Battery Back-up Switchover Voltage M48Z128V Expected Data Retention Time 10 2.5 V YEARS Min 4.5 4.2 2.8 Typ 4.6 4.3 2.9 3.0 Max 4.75 4.5 3.0 Unit V V V V
Note: 1. All voltages referenced to VSS. 2. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 4.75 to 5.5V, 4.5 to 5.5V, or 3.0 to 3.6V (except where noted). 3. At 25C; VCC = 0V.
VCC Noise And Negative Going Transients ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1F (see Figure 12) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values below VSS by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, ST recommends connecting a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). (Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface-mount).
Figure 12. Supply Voltage Protection
VCC VCC
0.1F
DEVICE
VSS
AI02169
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M48Z128, M48Z128Y, M48Z128V*
PART NUMBERING Table 12. Ordering Information Scheme
Example: M48Z 128Y -70 PM 1
Device Type M48Z
Supply Voltage and Write Protect Voltage 128 = VCC = 4.75 to 5.5V; VPFD = 4.5 to 4.75V 128Y = VCC = 4.5 to 5.5V; VPFD = 4.2 to 4.5V 128V(1) = VCC = 3.0 to 3.6V; VPFD = 2.8 to 3.0V
Speed -70 = 70ns (for M48Z128/Y) -85 = 85ns (for M48Z128/Y/V) -120 = 120ns (for M48Z128/Y/V)
Package(2) PM = PMDIP32
Temperature Range 1 = 0 to 70C
Note: 1. Contact Local Sales Office 2. The SOIC package (SOH28) requires the battery package (SNAPHAT (R)) which is ordered separately under the part number "M4Zxx-BR00SH" in plastic tube or "M4Zxx-BR00SHTR" in Tape & Reel form. Caution: Do not place the SNAPHAT battery package "M4Zxx-BR00SH" in conductive foam as it will drain the lithium button-cell battery.
For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. Table 13. SNAPHAT Battery Table
Part Number M4Z28-BR00SH M4Z32-BR00SH Description Lithium Battery (48mAh) SNAPHAT Lithium Battery (120mAh) SNAPHAT Package SH SH
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M48Z128, M48Z128Y, M48Z128V*
PACKAGE MECHANICAL INFORMATION Figure 13. PMDIP32 - 32-pin Plastic DIP Module, Package Outline
A
A1 S B e3 D e1
L eA
C
N
E
1 PMDIP
Note: Drawing is not to scale.
Table 14. PMDIP32 - 32-pin Plastic DIP Module, Package Mechanical Data
mm Symb Typ A A1 B C D E e1 e3 eA L S N Min 9.27 0.38 0.43 0.20 42.42 18.03 2.29 34.29 14.99 3.05 1.91 32 Max 9.52 - 0.59 0.33 43.18 18.80 2.79 41.91 16.00 3.81 2.79 Typ Min 0.365 0.015 0.017 0.008 1.670 0.710 0.090 1.350 0.590 0.120 0.075 32 Max 0.375 - 0.023 0.013 1.700 0.740 0.110 1.650 0.630 0.150 0.110 inches
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M48Z128, M48Z128Y, M48Z128V*
Figure 14. SOH28 - 28-lead Plastic Small Outline, battery SNAPHAT, Package Outline
A2 B e
A C eB CP
D
N
E
H A1 L
1 SOH-A
Note: Drawing is not to scale.
Table 15. SOH28 - 28-lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data
mm Symbol Typ A A1 A2 B C D E e eB H L N CP 1.27 0.05 2.34 0.36 0.15 17.71 8.23 - 3.20 11.51 0.41 0 28 0.10 Min Max 3.05 0.36 2.69 0.51 0.32 18.49 8.89 - 3.61 12.70 1.27 8 0.050 0.002 0.092 0.014 0.006 0.697 0.324 - 0.126 0.453 0.016 0 28 0.004 Typ Min Max 0.120 0.014 0.106 0.020 0.012 0.728 0.350 - 0.142 0.500 0.050 8 inch
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M48Z128, M48Z128Y, M48Z128V*
Figure 15. SH - 4-pin SNAPHAT Housing for 48mAh Battery, Package Outline
A1
A2 A A3
eA D
B eB
L
E
SHZP-A
Note: Drawing is not to scale.
Table 16. SH - 4-pin SNAPHAT Housing for 48mAh Battery, Package Mechanical Data
mm Symb Typ A A1 A2 A3 B D E eA eB L 0.46 21.21 14.22 15.55 3.20 2.03 6.73 6.48 Min Max 9.78 7.24 6.99 0.38 0.56 21.84 14.99 15.95 3.61 2.29 0.018 0.835 0.560 0.612 0.126 0.080 0.265 0.255 Typ Min Max 0.385 0.285 0.275 0.015 0.022 0.860 0.590 0.628 0.142 0.090 inches
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M48Z128, M48Z128Y, M48Z128V*
Figure 16. SH - 4-pin SNAPHAT Housing for 120mAh Battery, Package Outline
A1
A2 A A3
eA D
B eB
L
E
SHZP-A
Note: Drawing is not to scale.
Table 17. SH - 4-pin SNAPHAT Housing for 120mAh Battery, Package Mechanical Data
mm Symb Typ A A1 A2 A3 B D E eA eB L 0.46 21.21 17.27 15.55 3.20 2.03 8.00 7.24 Min Max 10.54 8.51 8.00 0.38 0.56 21.84 18.03 15.95 3.61 2.29 0.018 0.835 0.680 0.612 0.126 0.080 0.315 0.285 Typ Min Max 0.415 0.335 0.315 0.015 0.022 0.860 0.710 0.628 0.142 0.090 inches
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M48Z128, M48Z128Y, M48Z128V*
REVISION HISTORY Table 18. Revision History
Date May 1999 13-Apr-00 20-Jun-00 19-Jul-00 14-Sep-01 07-Nov-01 20-May-02 18-Nov-02 17-Sep-03 Rev. # 1.0 2.0 2.1 2.2 3.0 3.1 3.2 3.3 3.4 First Issue Document Layout changed; surface-Mount Chip Set solution added tGLQX changed (Table 8) M48Z128V added Reformatted; added temperature information (Table 5, 6, 8, 9, 10, 11) Remove chipset option from Ordering Information (Table 12) Modify reflow time and temperature footnotes (Table 3) Modifying SMT solution text (Figure 2, 5; Table 2) Remove references to M68ZXXX (obsolete) parts (Figure 5; Table 2); update disclaimer Revision Details
20/21
M48Z128, M48Z128Y, M48Z128V*
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2003 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com
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